DM74LSAN Synchronous 4-Bit Binary Counter With Asynchronous Clear. These synchronous, presettable counters feature an internal carry look-ahead for . DM74LSAN datasheet, DM74LSAN circuit, DM74LSAN data sheet: NSC – Synchronous 4-Bit Binary Counters,alldatasheet, datasheet, Datasheet. DM74LSAN datasheet, DM74LSAN circuit, DM74LSAN data sheet: FAIRCHILD – Synchronous 4-Bit Binary Counters,alldatasheet, datasheet.
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The ripple carry output thus enabled will produce a high- level output pulse with a duration approximately equal to the high-level portion of datadheet Q. The clear function for the DM74LSA is asynchro- nous; and a low level at the clear input sets all four of the flip-flop outputs LOW, regardless of the levels of clock, load, or enable inputs. Typical clock frequency 32 MHz. The function of the counter datasbeet enabled, dis- abled, loading, or counting will be dictated solely by the conditions meeting the stable set-up and hold times.
Enable P and enable T setup times are measured at t. The datwsheet Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Specify by appending the suffix letter “X” to the ordering code. Operating Free Air Temperature Range. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Internal look-ahead for fast counting.
Index of /datasheet
Clear Release Time Note 2. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous ripple clock counters. A buffered clock input triggers the four flip-flops on the rising positive-going edge of the clock input waveform. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings.
Clear Release Time Note 3. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without addi- tional gating. Typical propagation time, clock to Q output 14 dataeheet.
DM74LSAN Datasheet(PDF) – National Semiconductor (TI)
Search field Part name Part dm4ls161an. The gate output is connected to the clear input to synchronously clear the datasheeet to all low outputs. The input pulses are supplied by generators having the following characteristics: This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished with one external NAND gate. Clock Frequency Note 3. These dm47ls161an feature a fully independent clock circuit.
Typical power dissipation 93 mW. These counters are fully programmable; that is, the outputs may be preset to either level.
The device should not be operated at these limits. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the darasheet of the enable input.
Changes made to control inputs enable P or T or load that will modify the operating mode have no effect until clocking occurs. Devices also available in Tape and Reel. Carry output for n-bit cascading. Free Air Operating Temperature. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output.
The clear function for the DM74LSA is synchronous; and a low level at the clear inputs sets all four of the flip-flop outputs LOW after the next clock pulse, regardless of the levels of the enable inputs.
Clock Frequency Note 2. Synchronous operation is pro- vided by dataheet all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. These synchronous, presettable counters feature an inter- nal carry look-ahead for application in high-speed counting designs.
Vary PRR to measure f.